As data sources and numbers increase, correlation becomes a huge challenge.
As chip manufacturers turn to increasingly customized and complex heterogeneous designs to improve performance per watt, they also require lower defect rates and higher yields to help offset rising design and manufacturing costs.
Solving these problems requires huge efforts from multiple suppliers. There may be hundreds of process steps in fabs and packaging plants. As feature sizes continue to shrink, more elements are connected to a package, and some of these steps take longer and become more complicated. In turn, this makes it necessary to filter more and more manufacturing and packaging data and correlate various types of data from all these process steps and other processes.
"There are a lot of data sources," said Andrzej Strojwas, chief technology officer of PDF Solutions. "We are dealing with a wide range of data, from the in-situ real-time data of the equipment, to the information from online metrology, online defect detection, test chip data, and then the test data for wafer classification and final testing. And in aging. There is also New data from the internal structure of the chip can solve reliability problems. Everyone is using PVT sensors-process, voltage, temperature-they are essential to predict the performance of these chips in the field. There are also new types of sensors that can monitor due to acceleration Reliability risks caused by aging and changes in the entire assembly process and on-site mechanical stress."
The most important thing is that there are all kinds of equipment in any fab or packaging plant, some are new, some are not. As a result, the device collectively generates data of varying quality and quantity. What makes things more complicated is that usually not everything is under one roof. This makes timely sharing of data more important and more difficult, thereby exacerbating problems that have never been fully resolved in the foundry and packaging industry.
KLA’s senior director of strategic cooperation, Jairat, said: “These data about mold fit must be processed by multiple parties.” “Maybe this is an IDM, in this case, everything is under one roof. Or it may be a generation. Fabless design in a factory or OSAT is the most complex use case. We are trying to find a way that people can easily share a certain level of granularity in the data, but you don’t have to expose the entire process. In general , People have a deep understanding of what’s going on, but we usually don’t have full access to all this data because there is a lot of very proprietary information. The challenge is to skim only the safest layer while still being able to say, "This dice doesn't look like the others. "So you let the fab protect their process IP and any other types of confidential information they want to keep, but you are also confident that the information that the chip on this chip should be tested or burned out is a little different, or Run through system-level tests. People need to accept the idea that the entire industry needs this."
Others agree. Mike McIntyre, Director of Software Product Management at Onto Innovation, said: "Disjointed and disjointed data is a long-term problem, and being far away from real OEMs exacerbates this problem." "Most manufacturers have a model where at least some of the key parts are in their Done outside of the manufacturing environment. Historically, if you are an OEM, you at least have the ability to view all the data and access all the data available to you. Now, we need to create an infrastructure to integrate these data from different activities Integrate together. By providing content expertise, we can start adding different data so that you can form these relationships for analysis."
As the scale of the design continues to expand, this data disconnect becomes worse. Therefore, equipment testing is more fragmented, and is basically based on the divide-and-conquer method of developing chips. Supplementing the data from each process with the internal data of the working chip can provide a more complete view.
Marc Hutner, senior director of product marketing at proteanTecs, said: "In most cases, test engineers are just focusing on a stuck test or a very localized problem." "The exciting thing is that you can get data from inside the chip. And get alerts and insights from the entire chip or package. As more and more integrations happen, you can start looking for those types of relationships. You can still view it partially within a part of the mold, but you can go back to the mold level , You can even start to view it in the entire batch. So it’s multi-layered, and it’s also suitable for advanced packaging."
Packaging Challenges One major change in chip manufacturing is the increasing complexity of packaging. As the advantages of Moore's Law at each new node gradually weaken, more and more chip manufacturers have chosen more customized and increasingly heterogeneous designs and architectures. Delivering reliable chips on time is difficult enough, but putting multiple components in an advanced package can further complicate it.
"In the automotive industry, more than 50% of failures are caused by packaging," Strojwas said. "The assembly process itself is very complex and important for many industries, especially for automotive and military applications and data centers. So we need to track the source of a specific chip, which part of the wafer, but this is only the beginning of the story. You still You need to understand what happens to the substrate when you connect everything. In addition to the sensors that already exist, you now need to add additional types of sensors and complete traceability."
Complicated packaging brings a full range of challenges, from inspection and measurement, to the looping of data collected on site back to design and manufacturing.
CyberOptics CEO Subodh Kulkarni said: “Introducing more patterns, shapes and complexity at the package level.” Some of these are very complex packages. There are gaps of tens of micrometers between the chips, and there are some passive components among them. Now, somehow, we expect 100% inspection with good accuracy, which is not trivial. It's like trying to identify a few people in New York from a distance. Therefore, it becomes very complicated due to the size and how closely things are packed together. Now the back-end uses extremely complex front-end processes to process these packages and combine them. "
New uses of data, in turn, require more in-depth inspection and measurement, which often increases the time required to execute the relevant process steps and creates more data. Based on the yield and reliability indicators that are considered acceptable for any particular application or use case, it can have a significant impact on the entire process.
At the same time, deeper inspections have opened up new opportunities for using these data in areas such as atomic force microscopy (AFM). Ingo Schmitz, marketer of Brooke Nanosurface Technology, said: "Traditionally, with AFM, we deal with step height roughness, but we expand to CD (critical dimension), where we pursue smaller and smaller line/groove geometries. "Now we are turning to measuring more EUV-specific things, such as top line roughness due to off-axis lighting. Another very large area involves marking. A marking can cost hundreds of thousands of dollars, so marking Line repair and maintenance have become very important. When photomasks are used in exposure systems, they can be contaminated. So AFM is now used to identify defects and repair structures."
Figure 1: Contact holes in dual damascene trenches. Source: Brooke
Samsung, TSMC and Intel are using EUV lithography at the most advanced nodes, but the size is so small that some irregularities that were negligible in the past can now have a significant impact on performance and power over time.
"EUV blanks should have zero defects, but there is no such thing," Schmitz said. "What the company does is basically place patterns on EUV blanks so that they have the least amount of defects. When you enter the 10-20 nanometer domain, the defect size becomes more important, and AFM is the only one that stays in that dimension. system."
Almost all cutting-edge designs are customized in some way, and many designs are using options that they have never considered in the past, such as multiple accelerators and different types of memory.
"We are moving from a homogeneous monolithic silicon with a system-on-chip to a new paradigm,'I will build application-specific chips and integrate them into the system on the module, and be able to obtain the benefits of unique processing and put all the information in Together,'" McIntyre of Onto said. "In the past, you could test it evenly before it left the wafer. Now, you have to put all this additional assembly information together and integrate this data further. Just because everything passes the specification does not mean integration The solution passes the specification. This is the challenge."
The potential defects of material problems go far beyond surface inspection and measurement. All materials from substrates and RDLs to dielectric films need to be pure and applied with atomic precision.
Cristina Matos, Director of WLP Materials Technology at Brewer Science, said: “Permanent materials are subject to harsh conditions and there must be no chemical or mechanical changes during the expected life of the equipment.” “We focus on designing new materials and balancing the structure- Performance relationships to ensure that the material meets the expectations of accelerated aging, temperature cycling, and harsh storage conditions."
This has wide-ranging effects on the entire supply chain. Tom Brown, Executive Director of Manufacturing, Quality and Logistics at Brewer Science, said: "These requirements affect the manufacturing process in many ways." "First, as end user expectations increase, customer performance requirements become more extensive. For example, a A typical product acceptance certificate may have only required 10 items as a standard. Now, some customers list more than 200 requirements on the COA (Certificate of Analysis). In addition, the customer’s production line is becoming more and more sensitive to small changes in their products. This leads to the tightening of existing expectations. Specification restrictions and control restrictions tighten with each generation. The last consideration is that the manufacturing costs of customer products and Brewer Science products are getting higher and higher to meet the growing demand, further emphasis The need for robust waste/waste reduction and prevention programs.”
Purity and defect rate are also attracting more and more attention in various new application fields. This is obvious in power electronic devices, and until recently, they have largely received no attention because they use older process technologies. However, as they move into more secure applications (such as automobiles), they are also subject to the same scrutiny.
PDF's Strojwas said: "Silicon carbide can essentially be used as a substrate, and there are many applications where gallium nitride is mounted on a silicon carbide substrate." "Because this is mainly used in power electronics, or at least higher than the usual power requirements. , So you have to deal with heat propagation."
Strojwas pointed out that for high-performance system packaging, heat sinks are common. For true high-power mainframes, such as IBM's Z series, they now provide liquid cooling. Integration with the overall package is critical, and all of this data must be collected and checked, not only during wafer manufacturing, assembly, and testing, but also in the field. "
These types of concerns also extend to other substrates, especially in advanced packages where various materials may be used. CyberOptics’ Kulkarni said: “In terms of substrates, a lot of creative things are happening.” “They use different kinds of low-k materials to provide better electrical performance. We now have a more advanced one in our laboratory. A sample of the software package, they asked us to check it. On the one hand, there is this extremely shiny copper bump on a pillar about 20 microns, with this perfect hemisphere on the top. And we are using optical technology, so in fact you will To get a pixel that we can see in the camera, we try to use that pixel to infer the height of that bump. This is an extreme, it reflects everything perfectly. But the whole thing sits on a very diffuse substrate, there There is no reflection. Therefore, we are dealing with these issues, namely, how to design or project the dynamic range, where you have a low-k, high-diffusion substrate instead of a high-gloss, perfectly curved copper mirror. You need to design the dynamics of the projection scheme The range so that the detector does not oversaturate or see no signal at all. This is more of a problem in the field of substrates than in the field of wafers. This is a new field before the emergence of wafers. Substrates are becoming more and more complex , The size is getting smaller and smaller, which is changing the dynamics of optical inspection."
More choices, more data, and more problems. In the past, when the lead was dominated by the billion-unit design that was updated every two years, there was enough time and manufacturing volume to solve reliability problems relatively easily. But as the design becomes more personalized and smaller, the device itself becomes unique.
Synopsys memory interface IP product marketing manager Brett Murdock said: "One of the factors that help improve reliability is the number of times you do something. "In fact, we do the same thing, or almost the same thing, for every customer. This means that we are really good at it, and it has been proven in practice. You know it has millions of units in operation, so why is it different for us to sell HBM to this new AI customer for the first time? We don't need to reinvent anything. "
Although a variety of processing elements and a variety of memory options are available for optimization, it adds unknowns and more data to filter and correlate. This is obvious in the choice of DRAM. For example, sometimes the reason for choosing HBM is that there are fewer connection options and the possibility of errors is less.
"Using HBM devices, you will have lower power consumption and fewer physical interfaces," Murdock said. "Using DDR/GDDR/LPDDR and any of these interfaces, how to physically implement them on the SoC is the wild west. Do whatever you want. You can put a complete linear PHY on one side of the chip, and you can surround a corner , You can fold it up. There are countless ways to implement this physical interface."
This raises questions about reliability, and the longer these devices are used in the field, the more challenging it is to answer these questions.
Sathishkumar Balasubramanian, head of AMS verification products at Siemens EDA, said: “There are many monitors and sensors that become part of the circuit function to provide real-time data.” “What’s interesting is that we are not only seeing reliability in the automotive sector. We are even on the move. The industry has also seen it. We are dealing with a customer case where the storage they use in mobile devices should be designed to have a certain life span, 2.5 to 3 years, but people use their phones for 4 or 5 years. They don’t have With this in mind, this is mainly in terms of aging. In addition, especially in terms of memory, the number of read and write cycles they go through exceeds their design goals, which will also affect reliability."
In addition to meeting reliability specifications, the design team also found that they often had to exceed these specifications. “Whether it’s the fab or the design, designers have learned that what we really need is design, not over-design, while considering how much the model will be used and how we can make it more reliable,” said Ba La Subramanian. "So there is an aging effect, and you must also consider changes. How do you minimize variation? This starts from the building blocks of any circuit design. In design variants, we see many customers requesting this as a high Sigma requirement. People started early, and the entire design process started with library components. They wanted to ensure that these components were robust. For example, they wanted to ensure that for a given standard cell library, the process satisfies all the different PVT and larger ones. Range, even if you can’t verify it."
Aging has added a whole new level of attention, especially for safety-critical applications such as automobiles. "We have a series of applications around HTOL (High Temperature Working Life) testing, where you can start to understand the degree of aging of things from the inside," said Hutner of proteanTecs. "This extends to the field. So, as your new chip ages, you will start to see these effects. If it starts to wear out - you can predict when this will happen because you have an aging model, You can see if it deteriorates slowly or quickly-then you can say,'After three months, or when you leave your car in, you need to replace that module. This was impossible before."
Conclusion The slowdown in Moore's Law scaling and the sharp increase in the amount of processing required everywhere have prompted chip manufacturers and system companies to develop custom equipment. Now, they require these systems to be very reliable over a longer service life.
These are factors that usually do not mesh well. Therefore, the chip industry has been scrambling to find ways to combine more components in a smaller volume, and still produce more and more complex solutions. This requires the use of data collected from more sources and more process steps.
In short, the industry is once again out of its comfort zone, challenging old ways of doing things, including a proprietary attitude to data that needs to be shared in a disaggregated supply chain. None of this will happen easily, but as the need for reliability continues to grow—and the consequences of making mistakes become more serious, it must change.
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